- CXL 3.2 delivers a series of key improvements
- Security updates are a major focus for version 3.2
- CXL has become increasingly vital in the AI era
CXL Consortium has announced the release of its new Compute Express Link (CXL) 3.2 specifications, bringing a series of optimized features to the technology.
In his announcementthe consortium revealed that the upgraded specification would improve the monitoring and management capabilities of CXL memory devices, as well as the functionality of CXL memory devices for both operating systems and applications.
Security improvements are also a key talking point with the introduction of the Trusted Security Protocol (TSP).
What to expect from CXL 3.2
CXL plays a crucial role in how GPUs and CPUs interact with memory, helping to standardize communication between devices and reducing delays. All in all, this helps make systems faster and more efficient when processing large volumes of data.
With the advent of generative AI, CXL has become increasingly important given the rapid data processing requirements of applications, and this latest update will further improve previous specifications, especially in terms of monitoring and management CXL memory devices.
The new specification will include a new CXL Hot Page Monitoring Unit (CHMU) aimed specifically at streamlining memory tiering.
Likewise, the consortium revealed compatibility with PCIe Management Message (MMPT) as well as CXL online firmware enhancements.
Security improvements are a key focus of this latest update through TSP, the consortium noted, including new meta-bit storage features, expanded IDE protection, and improved compliance testing for interoperability.
Full backward compatibility with previous CXL specifications was also ensured by the consortium.
“We are excited to announce the release of the CXL 3.2 specification to advance the CXL ecosystem by providing improvements to the security, compliance, and functionality of CXL memory devices,” said Larrie Carr, President of the Consortium. CXL.
“The Consortium continues to develop an open and consistent interconnection and enable an interoperable ecosystem for heterogeneous memory and compute solutions.”
